1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly, a non-volatile semiconductor memory device in which a plurality of memory cells for storing data are arranged in a matrix.
2. Description of the Background Art
Electrically rewritable non-volatile semiconductor memory devices (hereinafter referred to as “non-volatile semiconductor memory devices”) have a property such that data is not lost when the device is powered off. Conventional non-volatile semiconductor memory devices have a structure which is described in, for example, “Furasshu Memori Gijyutsu Hando Bukku [Flash Memory Technical Handbook]” (Fujio Masoka, et al., 1993, Science Forum, p. 37). Hereinafter, conventional non-volatile semiconductor memory devices will be described.
In a conventional non-volatile semiconductor memory device, a rewrite operation is achieved by injection or ejection of electrons with respect to a floating gate of a transistor in a memory cell. The floating gate electrically floats. By injection or ejection of electrons with respect to the floating gate, the threshold voltage of a transistor is changed. A written state and an erased state of the transistor are distinguished from each other using the change of the threshold voltage. During a read operation, for example, a voltage read from the transistor of a memory cell is compared with a reference voltage by a differential amplifier to determine whether data is “1” or “0”.
However, in the above-described conventional non-volatile semiconductor memory device, the threshold voltage of the memory cell transistor is changed due to repetition of data rewrite, so that a difference between a voltage read from the memory cell transistor and the reference voltage is reduced. When the difference between the read voltage and the reference voltage becomes small, an error occurs in reading the data.
To solve this problem, a non-volatile semiconductor memory device has been proposed in Japanese Patent Laid-Open Publication No. H6-268180 (pp. 3–4, FIG. 1). Hereinafter, the non-volatile semiconductor memory device will be described with reference to FIG. 10. FIG. 10 is a diagram illustrating a cross-sectional structure of one cell of the non-volatile semiconductor memory device.
In the non-volatile semiconductor memory device of FIG. 10, two Nch transistors 901 and 902 are provided in each cell. One cell stores one-bit data. The non-volatile semiconductor memory device comprises a semiconductor substrate 1001, a source 1002, drains 1003 and 1004, tunnel oxide films 1005 and 1009, floating gates 1006 and 1010, gate oxide films 1007 and 1011, control gates 1008 and 1012, a source line 1013, a bit line 1014, a complementary bit line 1015, and a word line 1016.
The drain 1003, the source 1002 and the drain 1004 are appropriately spaced from each other on a surface of the semiconductor substrate 1001. The tunnel oxide film 1005 is provided between the source 1002 and the drain 1003 on the surface of the semiconductor substrate 1001. The floating gate 1006 is provided on the tunnel oxide film 1005. Further, the gate oxide film 1007 is provided on the floating gate 1006. Furthermore, the control gate 1008 is provided on the gate oxide film 1007. The tunnel oxide film 1009 is provided between the source 1002 and the drain 1004 on the surface of the semiconductor substrate 1001. The floating gate 1010 is provided on the tunnel oxide film 1009. Further, the gate oxide film 1011 is provided on the floating gate 1010. Furthermore, the control gate 1012 is provided on the gate oxide film 1011.
The source line 1013 is connected to the source 1002. The bit line 1014 is connected to the drain 1003. The complementary bit line 1015 which is complementary to the bit line 1014 is connected to the drain 1004. The word line 1016 is connected to the control gate 1008 and the control gate 1012. Note that the bit line 1014 and the complementary bit line 1015 are connected to a differential amplifier circuit (not shown) during a read operation.
An operation of the non-volatile semiconductor memory device thus constructed will be described. It is now assumed that, in the non-volatile semiconductor memory device, a state that data “1” is written refers to a state that electrons have been injected into the floating gate 1006 of the Nch transistor 901 while electrons have not been injected into the floating gate 1010 of the Nch transistor 902. A state that data “0” is written refers to a state that electrons have not been injected into the floating gate 1006 of the Nch transistor 901 while electrons have been injected to the floating gate 1010 of the Nch transistor 902.
Firstly, an operation of the non-volatile semiconductor device when writing data “1” will be described. To write data “1”, a power source voltage (e.g., 5 V) is applied to the bit line 1014, while the ground potential is applied to the complementary bit line 1015. A voltage (e.g., 12 V) which is higher than the power source voltage is applied to the word line 1016, while the ground potential is applied to the source line 1013.
When the voltages are applied in this manner, hot electrons are generated in the vicinity of the drain 1003, so that the hot electrons are injected into the floating gate 1006. On the other hand, hot electrons are not generated in the vicinity of the drain 1004, and therefore, electrons are not injected into the floating gate 1010.
With the above-described operation, the Nch transistor 901 is controlled into the written state, while the Nch transistor 902 is controlled into the erased state. As a result, data “1” is written into the non-volatile semiconductor device.
Next, an operation of the non-volatile semiconductor device when writing data “0” will be described. To write data “0”, the ground potential is applied to the bit line 1014, while the power source voltage (e.g., 5 V) is applied to the complementary bit line 1015. Further, a voltage (e.g., 12 V) which is higher than the power source voltage is applied to the word line 1016, while the ground potential is applied to the source line 1013.
When the voltages are applied in this manner, hot electrons are generated in the vicinity of the drain 1004, so that the hot electrons are injected into the floating gate 1010. On the other hand, hot electrons are not generated in the vicinity of the drain 1003, so that electrons are not injected into the floating gate 1006.
With the above-described operation, the Nch transistor 901 is controlled into the erased state, while the Nch transistor 902 is controlled into the written state. As a result, data “0” is written into the non-volatile semiconductor device.
Next, a data read operation of the non-volatile semiconductor device of FIG. 10 will be described. Firstly, a read operation when data “1” has been written will be described.
During the read operation, the power source voltage (e.g., 5 V) is applied to the word line 1016. A voltage (e.g., 2 V) which is lower than the power source voltage is applied to the bit line 1014 and the complementary bit line 1015.
In this situation, electrons have been injected in the floating gate 1006 of the Nch transistor 901. Therefore, the threshold voltage of the Nch transistor 901 is higher than the power source voltage. As a result, the Nch transistor 901 is controlled into an OFF state, so that a current does not flow from the drain 1003 to the source 1002. Therefore, substantially no voltage drop occurs in the bit line 1014.
On the other hand, electrons are not injected in the floating gate 1006 of the Nch transistor 902. Therefore, the threshold voltage of the Nch transistor 902 is lower than the power source voltage. As a result, the Nch transistor 902 is controlled into an ON state, so that a current flows from the drain 1004 to the source 1002. Therefore, a voltage drop occurs in the complementary bit line 1015.
The differential amplifier which is connected to the bit line 1014 and the complementary bit line 1015 detects a difference in voltage drop between the wire lines to determine the data. In this case, since data “1” is read out, the differential amplifier outputs a negative voltage.
Next, a read operation when data “0” has been written will be described. Note that a voltage which is applied to each wire line is similar to when data “1” has been written and will not be explained.
In this situation, electrons have not been injected in the floating gate 1006 of the Nch transistor 901. Therefore, the threshold voltage of the Nch transistor 901 is lower than the power source voltage. As a result, the Nch transistor 901 is controlled into an ON state, so that a current flows from the drain 1003 to the source 1002. Therefore, a voltage drop occurs in the bit line 1014.
On the other hand, electrons have been injected in the floating gate 1006 of the Nch transistor 902. Therefore, the threshold voltage of the Nch transistor 902 is higher than the power source voltage. As a result, the Nch transistor 902 is controlled into an OFF state, so that a current does not flow from the drain 1004 to the source 1002. Therefore, a voltage drop does not occur in the complementary bit line 1015.
The differential amplifier connected to the bit line 1014 and the complementary bit line 1015 detects a difference in voltage drop between these wire lines to determine the data. In this case, since data “0” is read out, the differential amplifier outputs a positive voltage.
As described above, in the non-volatile semiconductor memory device of FIG. 10, the data determination is performed using the difference between the voltages read from the two transistors included in one cell, but not using the reference voltage. As a result, errors in reading the data are reduced in the non-volatile semiconductor memory device of FIG. 10. Hereinafter, a more detailed description will be given.
In conventional non-volatile semiconductor devices, voltages read from the transistors of a memory cell are compared with a reference voltage to determine the data. The reference voltage is a voltage which has substantially an intermediate value between a voltage value read from a memory cell in the written state and a voltage value read from a memory cell in the erased state.
In contrast, in the non-volatile semiconductor device of FIG. 10, one of the transistors is controlled into the written state while the other is controlled into the erased state, to write data into a memory cell. To read data from a memory cell, a difference between voltages read from the two transistors is used to determine the data. Therefore, the voltage difference used in the data determination is a difference between a voltage read from a memory cell in the written state and a voltage read from the memory cell in the erased state. Therefore, in the non-volatile semiconductor memory device of FIG. 10, the voltage difference used for the data determination during a read operation is larger than that of the conventional non-volatile semiconductor memory device, so that an error is unlikely to occur in reading data.
In the non-volatile semiconductor memory device of FIG. 10, the voltage difference used for the data determination during the read operation is larger than that of the conventional non-volatile semiconductor memory device. Therefore, even when the amount of electrons to be injected into the floating gates 1006 and 1010 is smaller than that of the conventional non-volatile semiconductor device, an error occurs with a lower possibility in reading data. In other words, in the non-volatile semiconductor memory device of FIG. 10, even when the thickness of the tunnel oxide films 1005 and 1009 is reduced, an error is less likely to occur in reading data. Thus, the thickness of the tunnel oxide films 1005 and 1009 can be reduced, thereby achieving a high-speed and low-voltage operation of the non-volatile semiconductor memory device.
However, in the non-volatile semiconductor memory device of FIG. 10, an erase operation in which injected electrons are extracted out from the floating gate 1006 of the Nch transistor 901 or the floating gate 1010 of the Nch transistor 902 is required for rewriting of data “1” into data “0” or data “0” into data “1”. Therefore, in the non-volatile semiconductor memory device of FIG. 10, it disadvantageously takes a long time to rewrite data. Hereinafter, for example, the rewriting of data “1” into data “0” will be described in detail.
When data “1” is stored in a memory cell, electrons have been injected in the floating gate 1006 of the Nch transistor 901, while electrons have not been injected in the floating gate 1010 of the Nch transistor 902. In this case, when an operation of writing data “0” into a memory cell is performed without extracting out the electrons injected in the floating gate 1006 (erase operation), electrons are injected into both the floating gate 1006 and the floating gate 1010. As a result, the differential amplifier can no longer determine data stored in the memory cell when reading out the data. Therefore, data in the memory cell needs to be erased before rewriting the data in the memory cell. Therefore, it disadvantageously takes a long time to rewrite data in the non-volatile semiconductor memory device of FIG. 10.